This invention relates to information processing systems including arithmetic control units capable of pefetching user's instructions from main memory and, more particularly, a unit of this type which is formed as a single large-scale semiconductor integrated circuit chip.
Owing to recent advancements in semiconductor techniques, the arithmetic control unit which constitutes a major part of information processing systems can be provided as a single very large scale integrated semiconductor element (hereinafter referred to as VLSI). With the implementation of the arithmetic control unit in VLSI, improved reliability, increased compactness and improved price versus performance ratios can be expected. However, use of VLSI also causes such problems as control of package pin count, limitation on power consumed and limitations upon capacity of accomodation and performance. To solve these problems, the future development of techniques for applying VLSI is a great concern. Of these technical problems, this invention relates to the problems of limitations imposed upon the accommodation capacity and performance.
Information processing systems in which user's instructions are decoded and executed under microprogram control include those in which user's instructions are prefetched for the purpose of high speed processing. An arithmetic control unit which is a component element of such an information processing system usually includes a prefetch control mechanism and a plurality of instruction buffer stages where a plurality of different prefetched user instructions can be stored. It further includes an instruction register for holding the instruction being executed, a location counter for holding the location of the instruction to be executed next, a memory address register for holding the memory address of the next operard to be fetched and a prefetch instruction location counter for holding the location of the user instruction to be prefetched next. The prefetch control mechanism permits successive user instructions to be fetched from main memory and stored in successive instruction buffer stages. The prefetched instructions stored in instruction buffer are read out in the order of their storage when desired.
It is now assumed that contents in addresses (alpha+4), (alpha+6), (alpha+8) and (alpha+A) of main memory have been stored in the instruction buffers as shown in FIG. 1 and that an instruction in address alpha which has already been read into the instruction buffer register is a "store" instruction for overwriting the contents of, for instance, the address (alpha+4) of main memory. After the "store" is executed, the instruction in the instruction buffer is no longer the same as the contents of the address (alpha+4) of main memory. Therefore, if the program is executed without any correction, a malfunction results. For this reason, as soon as the contents in contents of the address (alpha+4) of main memory is overwritten, the contents of the instruction buffers are rendered ineffective. Likewise, the contents of the instruction buffers are rendered ineffective when the program is branched. In either case, therefore, it is necessary to re-fetch the contents of the instruction buffers.
In some systems, whenever main memory is written into, as by the aforementioned "store" instruction, the destination address is compared with both the contents of the location counter and that of the prefetch instruction location counter and, if the contents of the destination address is equal to or greater than the location counter contents and smaller than the prefetch instruction location counter contents, the contents of the instruction buffers are rendered ineffective. In other systems, the contents of the instruction buffers are rendered ineffective automatically and without any comparison.
In the case of the first type, in order to obtain high speed processing, two comparators are required. The provision of two comparators in VLSI, however, introduces difficulties particularly in wiring inside the chip and is therefore not recommended. With the second type, the processing performance obtainable is inferior.
In another aspect, in an arithmetic control unit formed as a single chip (hereinafter referred to as one-chip CPU) as mentioned above, in which a plurality of internal instruction prefetch buffer stages are provided in order to reduce the time required for instruction fetches from an external main memory, an address matching mechanism is provided outside the chip. Such an address matching mechanism functions such that when the one-chip CPU makes access to a memory address preset by the operator or the like, it produces an interrupt instruction to stop the program under execution upon detecting a coincidence of addresses, and it is used when it is desired to interrupt a program at a desired step. For the mechanism to be useful, the execution stop must be brought about when the one-chip CPU is about the execute the data processing contents in the preset address. With the construction as described above, however, the one-chip CPU always undertakes a prefetch. It is therefore possible that the coincidence of addresses is detected at the time when access is made to the main memory for prefetching an instruction, which may be earlier than the time the instruction is to be executed. Therefore, timing is not proper if an address stop takes place at the time of detection of the coincidence of addresses, and proper address matching is not fulfilled. Instead, it is necessary to produce an interrupt upon detection of coincidence of addresses but at the time a prefetched instruction is executed, i.e., the time at which the instruction is output from the prefetch instruction buffers. Thus, it has been desired to effectively realize address matching which can bring about an address stop at the proper time within the physical restrictions imposed upon a one-chip CPU.
In a further aspect, in a one-chip CPU, in addition to providing a plurality of internal instruction prefetch buffer stages in order to reduce the time required for an instruction fetch from an external main memory and permit high speed processing, it is thought to provide an external address conversion mechanism (address conversion table) for expanding the address space of main memory. In such a construction, when a segment in the address conversion table is specified according to logical address data from the one-chip CPU, the main memory may be accessed according to a physical address corresponding to the specified segment. If the segment is undefined, that fact must be noted at the time the access is attempted. Since the one-chip CPU undertakes prefetching of instructions as mentioned earlier, it is already storing some prefetch instructions in its internal prefetch instruction buffers for execution. Therefore, the time at which the address conversion table is consulted, and the time at which the accessed instruction is actually output from the buffers and executed, are different from each other. This means that even if an illegal address is detected through consultation of the address conversion table, the production of an illegal address interrupt at that time would not be timed properly. Accordingly, in such a construction the one-chip CPU must include a mechanism for properly timing illegal address interrupts, and means for effectively realizing such a mechanism within the physical limitations imposed upon the chip.